Frequency-agile clocking has emerged as an effective power-conservation technique in mobile devices. Ideally, the system clock that serves as a primary timing reference for functional operations is switched instantly between various frequencies, scaling power consumption according to the work at hand. In practice, latency (delay) between frequency shifts can be incurred at each frequency transition as frequency-multiplier circuitry stabilizes the system clock at its new frequency following each change.
Unfortunately, conventional phase-locked loop (PLL) multipliers require relatively long re-lock times following frequency changes and thus, despite a potentially broad input frequency range, incur latency penalties which should be avoided in a frequency-agile system if the system is to attempt to use the lowest frequency possible as a method of power conservation. Conversely, injection-locked oscillators exhibit fast lock times, but tend to have a narrow input frequency range and thus limited frequency agility.